Zhiyi Hong
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7be3062c51
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[Docs] unify phase experiment archive naming
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2026-07-31 17:00:22 +08:00 |
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Zhiyi Hong
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66d1db8581
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[Docs] link Phase 2 code walkthrough
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2026-07-31 16:01:57 +08:00 |
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Zhiyi Hong
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4892c0b14d
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[Docs] document final Phase 2 attribution workflow
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2026-07-31 15:47:10 +08:00 |
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Zhiyi Hong
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337195254a
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[Docs] summarize Phase 2 hardware attribution
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2026-07-31 13:50:27 +08:00 |
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Zhiyi Hong
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daa4221128
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[Feat] add DSV4-Pro two-node SGLang hardware attribution
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2026-07-31 12:18:34 +08:00 |
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Zhiyi Hong
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25418ec174
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[Docs] record completed DSV4-Pro Phase 1 quick map
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2026-07-30 23:13:48 +08:00 |
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Zhiyi Hong
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75182c6ede
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[Feat] add Phase 1 sanity gate
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2026-07-30 18:59:14 +08:00 |
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Zhiyi Hong
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0d3dd86519
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[BugFix] enforce RDMA transport for DSV4-Pro TP16 quick map
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2026-07-30 18:17:33 +08:00 |
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Zhiyi Hong
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595bdde5d7
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[Docs] audit DSV4-Pro TP16 TTFT benchmark semantics
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2026-07-30 16:41:11 +08:00 |
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